Benchmark RadarRTL-Bench
RTL-BenchLS evaluates LLMs on RTL design generation and reasoning, containing over 10,000 formally verified Verilog designs. Tasks include specification-to-RTL generation, round-trip reasoning, masked-content reasoning, and repository-issue reasoning. All tasks are verified via formal equivalence checking without manual testbenches.
- Released
- 2026-06-08
- Readiness
- Paper only
- Primary field
- Industrial & Engineering
Why it matters
Existing RTL benchmarks are small and saturate with frontier models. RTL-BenchLS provides a large-scale, challenging benchmark with self-supervised tasks, enabling tracking of progress on complex hardware design reasoning and generation.
Motivation
LLM-based RTL generation and reasoning is a promising direction for hardware design automation.
Primary resources
Benchmark Radar records only publicly supported details and links back to primary sources for verification.